ATMEGA3250V-8AI【PDF 21/29 页】IC AVR MCU 32K 8MHZ 100TQFP

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PCA9698

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Product data sheet

Rev. 3 — 3 August 2010

28 of 48

NXP Semiconductors

PCA9698

40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

The programming becomes effective at the Acknowledge.

If more than 1 byte is written, previous data is overwritten.

Fig 18. Write to the output structure configuration, all bank control, or mode selection

002aab947

S A6 A5 A4 A3 A2 A1 A0 0 A

slave address

R/W

START condition

command register

AI = 'don't care'

acknowledge

from slave

DATA

acknowledge

from slave

acknowledge

from slave

STOP condition

SDA

01010 D1 D0

00 for output structure configuration programming

01 for all bank control register programming

10 for mode selection register programming

If AI = 0, the same register is read during the whole sequence.

If AI = 1, the register value is incremented after each read. When the last register bank is read, it rolls over to the first byte of the

category (see category definition in Section 7.3 “Command register”).

The INT signal is released only when the last register containing an input that changed has been read. For example, when

IO2_4 and IO4_7 change at the same time and an Input Port register read sequence is initiated, starting with IP0, INT is

released after IP4 is read (and not after IP2 is read).

Fig 19. Read from Input Port, Output Port, I/O Configuration, Polarity Inversion, or Mask interrupt registers

002aab948

S A6 A5 A4 A3 A2 A1 A0 0 A

slave address

R/W

START condition

command register

AI = 1

acknowledge

from slave

no acknowledge

from master

acknowledge

from slave

STOP condition

SDA

0 D5 D4 D3 D2 D1 D0

repeated START

condition

A6 A5 A4 A3 A2 A1 A0

slave address

1 A

R/W

acknowledge

from slave

data from register

DATA

acknowledge

from master

first byte

by D4 D3 D2 D1 D0

data from register

DATA

second byte

data from register

DATA

last byte

D[5:0] = 00 1000 for Output Port register bank 0

D[5:0] = 01 0000 for Polarity Inversion register bank 0

D[5:0] = 01 1000 for Configuration register bank 0

D[5:0] = 00 0000 for Input Port register bank 0

D[5:0] = 10 0000 for Mask Interrupt register bank 0

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